MAX5938LEEE+【PDF 21/26 页】IC HOT-SWAP CTRLR -48V 16-QSOP

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Sheet目录43

17页 18页 19页 20页 [21页]22页 23页 24页 25页

Power-Up-to-Fault-Management Fault:

1) Same as step 1 above. [GATE turn-on]

2) Same as step 2 above. [V

OUT

ramp]

3) GATE ramps to 90% of full enhancement while

OUT

remains above 74% V

, at which point the

GATE is rapidly pulled to V

and fault manage-

ment is initiated. [Fault management]

GATE Cycle During V

Step

A step GATE cycle occurs only after a successful

power-up GATE cycle to full enhancement occurs and

as a result of a positive V

step (all voltages are

relative to V

Step-to-Full-Enhancement Fault:

1) A V

step occurs resulting in STEP_MON rising

above STEP

before V

OUT

rises above V

. [Step

detection]

2) After a step is detected, V

OUT

rises above V

response to the step. When V

OUT

rises above V

GATE is immediately pulled to V

, rapidly turning

off the power MOSFET. GATE is held at V

for

350祍 to damp any ringing. Once GATE is pulled to

, the gate cycle has begun and STEP_MON can

safely drop below STEP

and successfully com-

plete a step GATE cycle to full enhancement without

initiating fault management. [GATE pulldown]

3) Following the 350祍 of GATE pulldown, GATE is

allowed to float for 650祍. At this point, the GATE

begins to ramp with 52礎 charging the gate of the

power MOSFET. [GATE turn-on]

4) When GATE reaches the gate threshold voltage of

the power MOSFET, V

OUT

begins to ramp down

toward the new lower V

. In the interval where

GATE is below the MOSFET threshold, the MOSFET

is off and V

OUT

will droop depending on the RC

time constant of the load. [V

OUT

ramp]

5) When V

OUT

ramps below 74% V

, the GATE pulls

rapidly to full enhancement and the step GATE

cycle is complete. If STEP_MON remains above

STEP

when GATE has ramped to 90% of full

enhancement and V

OUT

remains above 74% of V

GATE remains at 90% and is not pulled to full

enhancement. In this condition, if V

OUT

drops below

74% of V

before STEP_MON drops below

STEP

, GATE is rapidly pulled to full enhancement

and the step GATE cycle is complete. PGOOD

remains asserted throughout the step GATE cycle.

[Full enhancement]

Step-to-Fault-Management Fault:

1) Same as step 1 above. [Step detection]

2) Same as step 2 above. [GATE pulldown]

3) Same as step 3 above. [GATE turn-on]

4) Same as step 4 above. [V

OUT

ramp]

5) If STEP_MON is below STEP

when GATE ramps

to 90% of full enhancement and V

OUT

remains

above 74% V

CB,

GATE is rapidly pulled to V

Fault management is initiated and PGOOD is de-

asserted. If STEP_MON is above STEP

when

GATE ramps to 90% of full enhancement and V

OUT

remains above 74% of V

, GATE remains at 90%.

It is not pulled to full enhancement nor is it pulled to

. In this condition, if V

OUT

drops below 74% of

before STEP_MON drops below STEP

GATE is rapidly pulled to full enhancement and a

fault is avoided. Conversely, if STEP_MON drops

below STEP

first, the GATE is rapidly pulled to

, fault management is initiated, and PGOOD is

deasserted. [Fault management]

It should be emphasized that while STEP_MON remains

above STEP

the current fault management is

blocked. During this time it is possible for there to be

multiple events involving V

OUT

rising above V

then

falling below 74% V

. In each of these events, when

OUT

rises above V

, a full GATE cycle is initiated

where GATE is first pulled low then allowed to ramp up.

Then finally, when V

OUT

conditions are met, it will be

fully enhanced.

GATE Cycle During Momentary Overvoltage

An OV GATE cycle occurs only after a successful

power-up GATE cycle to full enhancement and as a

result of a momentary excursion of OV above the OV

threshold voltage. An OV GATE cycle does not result in

an OV fault unless OV remains above the threshold for

more than 1.5ms (all voltages are relative to V

OV GATE Cycle to Full enhancement:

1) When OV rises above the OV threshold voltage,

GATE is immediately pulled to V

, rapidly turning

off the power MOSFET. GATE is held at V

indefi-

nitely while OV is above the OV threshold voltage. It

is held for an additional 350祍 to damp any ringing.

[GATE pulldown]

2) Following the GATE pulldown, GATE is allowed to

float for 650祍. At this point, the GATE begins to

ramp with 52礎 charging the gate of the power

MOSFET. [GATE turn-on]

-48V Hot-Swap Controller with V

Step Immunity,

No R

SENSE

, and Overvoltage Protection

______________________________________________________________________________________ 21

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